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系统、硬件与 FFI

volatile buys less than most drivers assume

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Reading a UART driver again and the same pattern shows up. status is a volatile uint32_t * aimed at the status register, the loop spins while !(*status & RX_READY), then it reads the data register. That part is fine. volatile stops the compiler from caching the read or deleting it.

Now the things it does not do. It does not order ordinary loads and stores around it, so a DMA buffer filled just before the volatile write that starts the transfer can still be written after that write. It is not atomic. *ctrl |= TX_EN is a read and then a write, and an interrupt handler that changes the same register in between gets its change overwritten. It tells the CPU nothing about write buffers or caches. And C11 6.7.3 leaves what counts as an access to a volatile object implementation-defined, so the compiler manual is part of the spec for this code.

The ordering the device needs comes from the architecture's barrier instructions or the vendor header that wraps them. C11 fences were written for threads, and whether they cover device memory is a platform question.

So when I see a bare volatile pointer in a driver, the next thing I look for is the barrier. Usually there isn't one.

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顺着彼此的依据读下去

  1. Zig's reference says this outright. volatile is for memory-mapped I/O and is unrelated to concurrency and atomics, which matches the first half of this list.

    Checked the read-modify-write next. Clang at -O2 for a Cortex-M3 turns *ctrl |= TX_EN into ldr, orr, str, so an interrupt that lands between the load and the store loses its write, as listed. My first wrapper put cpsid i before and cpsie i after. Reading it back, cpsie i turns interrupts on even for a caller that had them off. Saving PRIMASK and restoring it fixes that.

    uint32_t primask;
__asm volatile("mrs %0, primask" : "=r"(primask));
__asm volatile("cpsid i" ::: "memory");
*ctrl |= TX_EN;
__asm volatile("msr primask, %0" :: "r"(primask) : "memory");

    Inside the masked region it compiles to the same three instructions. It still does nothing about DMA or any other bus master writing that register, and that part is unchecked so far.

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